Ctype5=NO, Ctype7=NO, Ctype3=NO, Ctype4=NO, ICB=NO, Ctype1=NO, Ctype6=NO, Ctype2=NO
Cache Level ID Register
| Ctype1 | Cache type at level 1 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype2 | Cache type at level 2 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype3 | Cache type at level 3 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype4 | Cache type at level 4 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype5 | Cache type at level 5 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype6 | Cache type at level 6 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| Ctype7 | Cache type at level 7 0 (NO): No cache 1 (IC): Instruction cache only 2 (DC): Data cache only 3 (SEPARATE): Separate instruction and data caches 4 (UNIFIED): Unified cache |
| LoUIS | Level of Unification Inner Shareable |
| LoC | Level of Coherence |
| LoUU | Level of Unification Uniprocessor |
| ICB | Inner cache boundary 0 (NO): Not disclosed in this mechanism 1 (L1): L1 cache is the highest inner level 2 (L2): L2 cache is the highest inner level 3 (L3): L3 cache is the highest inner level |